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126

XMEGA A [MANUAL]

8077I–AVR–11/2012

vector. The interrupt vector is normally a jump to the interrupt handler; the software routine that handles the interrupt.

After returning from the interrupt handler, program execution continues from where it was before the interrupt occurred.

One instruction is always executed before any pending interrupt is served.

The PMIC status register contains state information that ensures that the PMIC returns to the correct interrupt level when

the RETI (interrupt return) instruction is executed at the end of an interrupt handler. Returning from an interrupt will return

the PMIC to the state it had before entering the interrupt. The status register (SREG) is not saved automatically upon an

interrupt request. The RET (subroutine return) instruction cannot be used when returning from the interrupt handler

routine, as this will not return the PMIC to its correct state.

12.4

Interrupts

All interrupts and the reset vector each have a separate program vector address in the program memory space. The

lowest address in the program memory space is the reset vector. All interrupts are assigned individual control bits for

enabling and setting the interrupt level, and this is set in the control registers for each peripheral that can generate

interrupts. Details on each interrupt are described in the peripheral where the interrupt is available.

All interrupts have an interrupt flag associated with it. When the interrupt condition is present, the interrupt flag will be set,

even if the corresponding interrupt is not enabled. For most interrupts, the interrupt flag is automatically cleared when

executing the interrupt vector. Writing a logical one to the interrupt flag will also clear the flag. Some interrupt flags are

not cleared when executing the interrupt vector, and some are cleared automatically when an associated register is

accessed (read or written). This is described for each individual interrupt flag.

If an interrupt condition occurs while another, higher priority interrupt is executing or pending, the interrupt flag will be set

and remembered until the interrupt has priority. If an interrupt condition occurs while the corresponding interrupt is not

enabled, the interrupt flag will be set and remembered until the interrupt is enabled or the flag is cleared by software.

Similarly, if one or more interrupt conditions occur while global interrupts are disabled, the corresponding interrupt flag

will be set and remembered until global interrupts are enabled. All pending interrupts are then executed according to their

order of priority.

Interrupts can be blocked when executing code from a locked section; e.g., when the boot lock bits are programmed.

This feature improves software security. Refer to “Memory Programming” on page 353 for details on lock bit settings.

Interrupts are automatically disabled for up to four CPU clock cycles when the configuration change protection register is

written with the correct signature. Refer to “Configuration Change Protection” on page 13 for more details.

12.4.1 NMI – Non-Maskable Interrupts

Which interrupts represent NMI and which represent regular interrupts cannot be selected. Non-maskable interrupts

must be enabled before they can be used. Refer to the device datasheet for NMI present on each device.

An NMI will be executed regardless of the setting of the I bit, and it will never change the I bit. No other interrupts can

interrupt a NMI handler. If more than one NMI is requested at the same time, priority is static according to the interrupt

vector address, where the lowest address has highest priority.

12.4.2 Interrupt Response Time

The interrupt response time for all the enabled interrupts is three CPU clock cycles, minimum; one cycle to finish the

ongoing instruction and two cycles to store the program counter to the stack. After the program counter is pushed on the

stack, the program vector for the interrupt is executed. The jump to the interrupt handler takes three clock cycles.

If an interrupt occurs during execution of a multicycle instruction, this instruction is completed before the interrupt is

served. See Figure 12-2 on page 127 for more details.

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